1. Field of the Invention
The field of the invention is data processing, or, more specifically, methods and apparatus for measuring control signal timing for synchronous dynamic random access memory (‘SDRAM’).
2. Description of Related Art
The SDRAM memory bus is a synchronous bus having both data signals and clock signals. Data signals are called ‘DQ,’ and the clock is called a ‘strobe’ and labeled ‘DQS’ to differentiate it from the system clock signal which is also one of the SDRAM control signals. The SDRAM memory bus is bidirectional, driven by a memory controller during READ operations, driven by the SDRAM during WRITEs. The timing relationship between DQ and DQS is part of the official JEDEC SDRAM specification, therefore always a subject of test. This timing relationship, however, is very difficult to measure in test because the timing between DQ and DQS varies between READ and WRITE operations. In READs, the memory controller drives the DQS signal in phase with the DQ signal. In WRITEs, the SDRAM device drives the DQS signal out of phase with the DQ signal. When a sequence of READ and WRITE operations is captured and displayed on a test oscilloscope, therefore, the result is the jumbled, difficult-to-read display illustrated in FIG. 1.
FIG. 1 sets forth a line drawing of a test oscilloscope (118) with an oscilloscope display (120) upon which are shown test traces for DQ (102) and DQS (104), with the traces so overlapping and jumbled that it is not possible to measure the control signal timing. In FIG. 1, the scope trace and capture is triggered on a system clock, which is also an SDRAM bus control signal, and the signals captured, in addition to the memory bus signal DQS, include a test sequence of DQ data signals that includes both READ operations and WRITE operations. The oscilloscope (118) therefore captures and displays both phases of DQS, one for READs and one for WRITES as well as two phases of DQ. The result is the difficulty shown.
Prior art clarifies the scope display by writing a program to loop a series of consecutive READ operations only or a series of consecutive WRITE operations only while performing timing measurements. Looping only WRITE or only READ operations, however, risks missing signal quality issues that exist only during bus turn around time from WRITE to READ or from READ to WRITE. Prior art has also attempted to clarify the test display by using a separate logic analyzer to separate the signals, but this approach requires additional, expensive equipment and expertise.